1. Field of the Invention
The invention relates in general to a semiconductor memory device. More particularly, this invention relates to a semiconductor memory device with a function of prompt equalization of a dataline pair.
2. Description of the Related Art
According to the advancement of computer technology, the operation speed of computers is faster and faster. Apart from improving the processing speed of central process unit (CPU), the efficiency of other components in the computer has to be promoted as well. For example, in addition to the enhancement of data access speed, the controlling method of a dynamic random access memory (DRAM) has to be updated into a fast page mode and an extended data out mode, or even a synchronized DRAM (SDRAM).
In a conventional semiconductor memory device, while a pulse signal, that is, a write recovery control signal, for a write operation is triggered, the bit line pairs BL and BLB are both precharged up to a predetermined voltage. The bit lines BL and BLB are in a complementary relationship.
Under the precharging state, while any word line WL1 to WLn is selected by a row select signal, plus the column select signal and the write pulse signal are triggered, one of the dataline pair DL or DLB is pulled down to a low voltage level (normally a ground level GND). The corresponding bit line BL or BLB is also pulled down to a low level, while other bit line BL or BLB is pulled up to a high voltage level (normally a supplied voltage VCC). Thus, data can be written into a memory cell. The memory device then prepares a next write cycle according to the write recovery control signal, so that the bit lines BL and BLB are back to the precharging state.
Typically, during a read/write operation, one of the datalines DL and DLB is charged up to a high level VCC, while the other one is discharged to a low level GND. In addition, during a standby mode, both the datalines DL and DLB are precharged to a voltage of VCC/2.
Therefore, for a command of a semiconductor memory device such as an SDRAM, in the normal access operation, equalization is very crucial. An equalization command is equivalent to charging the bit line with a voltage of VCC/2.
For example, when an active command is executed, a proper word line driver is activated. The word line driver turns on the word line transistor, and charges of memory cell are then distributed to the bit line. The signal of charges on the bit line is then amplified by the bit sense amplifier. A threshold voltage of VCC/2 thus enables the bit line sense amplifier to amplify this signal to full swing within a shortest time. A read/write command is then activated. After turning off the word line, the equalization means is turned on, so that the charges on both the datalines DL and DLB can be shared thereby.
As shown in FIG. 1, a circuit diagram of a conventional memory device is illustrated. The circuit includes a memory cell array 100, a bit line sense amplifier 110, an equalization means 120 and a dataline sense amplifier 130. The memory cell array 100 is connected to the bit line sense amplifier 110 via the bit line pair BL and BLB. The equalization means 120 and the dataline pair sense amplifier 130 are connected across the dataline pair DL and DLB. The equalization means 120 is used to equalize the voltage levels of the dataline pair DL and DLB.
As described as above, after the read/write operation, the system enters a standby mode. The equalization means 120 is turned on to equalize the datalines DL and DLB, that is, the datalines DL and DLB are to share the total charges on thereon. Provided that the datalines DL and DLB reach a full swing before the aforementioned state, the total charges on the datalines DL and DLB are shared into VCC/2. Under such normal equalization mode, a weak voltage VP (=VCC/2) generator connected to the equalization means 120 can not provide a strong current force to the whole memory array, and thus is not to be damaged. The weak voltage VP generator is used to provide a required voltage (VCC/2) to the equalization means 120. However, during the equalization mode, under the circumstance that the datalines DL and DLB can not reach a full swing, that is, if the voltage of the datalines DL and DLB is higher than VCC/2, the weak voltage VP will be damaged thereby.
The conventional datalines equalization includes:
Step 1: turning off the word line. PA1 Step 2: turning on the equalization means.
Since the memory has a very high speed of operation, the data sense amplifier 130 has only a very transient time to amplify the signal of the datalines DL and DLB. Therefore, a full swing of the signal of the dataline pair DL and DLB can not be achieved. In the above-mentioned equalization mode, the voltage of the dataline pair DL and DLB are higher or lower than VCC/2. In other words, the higher the speed of a memory circuit is, the higher the voltage of the datalines DL and DBL is. This high voltage will damage the weak voltage VP (=VCC/2) generator.
In addition, if the voltage of the dataline pair DL and DLB can not be reached during the transient equalization mode, the data read or written into the memory cell will be incomplete before the next read/write command is given.